1. Field of the Invention
The present invention generally relates to a built-in self repair (BISR) circuit for a memory and a method thereof, in particular, to a BISR circuit for a multi-port memory and a method thereof.
2. Description of Related Art
When an on-chip circuit contains multiple memories, testing of these memories will become a big problem. All the input and output terminals of the memories have to be connected out of the chip if an external device is used for testing the memories, such an enormous circuit layout not only takes up a lot of chip surface and increases the complexity of the circuit layout but is unrealistic with only limited number of chip pins. Thus, a concept of built-in self test (BIST) is provided, which is to fabricate a testing circuit and the memories to be tested on the same chip so that the input and output terminals of the memories do not have to be connected out of the chip for merely testing purpose. A built-in self repair (BISR) technique has been developed based on the BIST technique after repairable memory was invented.
FIG. 1 illustrates a conventional BISR circuit for a memory. A self tester 102 tests a repairable memory 101. If a fault occurs, the self tester 102 sends the location of the fault to a redundancy element analyzer 103, and the redundancy element analyzer 103 then analyzes the fault information detected by the self tester 102 and sends an optimal repair plan to the repairable memory 101. The repairable memory 101 then repairs the faulty column or row with a built-in redundancy element (i.e. a redundancy column and/or a redundancy row) according to this optimal repair plan.
According to the conventional BISR technique, a faulty column or row is repaired straightaway once the fault is detected in a memory, regardless of single-port or multi-port memory. This is feasible to a single-port memory for the detected fault location in the single-port memory is the actual defect location. However, as to a multi-port memory, the detected fault location may not be the actual defect location if a port-specific fault is generated during the test of the self tester 102, as illustrated in FIG. 2.
FIG. 2 illustrates three memory cells Cell0˜Cell2 and related word lines and bit lines in a multi-port memory. Referring to FIG. 2, the multi-port memory has two ports which are respectively port A and port B. The column addresses of the memory cells Cell0˜Cell2 are all 0, and the row addresses thereof are respectively 0˜2. The bit value stored in Cell0 and Cell1 is 1, and the bit value stored in Cell2 is 0. ABL0 is a bit line corresponding to port A, and BBL0 is a bit line corresponding to port B. AWL0 is a word line corresponding to port A and row address Addr0, BWL0 is a word line corresponding to port B and row address Addr0, AWL1 is a word line corresponding to port A and row address Addr1, and so on. As shown in FIG. 2, a short circuit defect exists between the word lines AWL1 and BWL2.
When a testing program reads port B at row address Addr0 and port A at row address Addr1 at the same time, the word lines BWL0 and AWL1 are both enabled, and meanwhile, the word line BWL2 is also enabled due to the short circuit defect between the word lines AWL1 and BWL2. Thus, the data stored in Cell1 is output to the bit line ABL0, and the data stored in Cell0 and Cell2 are output to the bit line BBL0 at the same time. Since two different values are output to the bit line BBL0 at the same time, the value read from port B at row address Addr0 is faulty. However, the actual defect is not located at the row address Addr0 detected by the testing program but at row addresses Addr1 and Addr2.
In this case, the actual defect cannot be repaired by repairing the faulty row, and it will also be a waste of the redundancy element and cause a yield loss.
On the other hand, the situation described above will not happen to short circuit defect between bit lines, namely, the correct location of a short circuit defect between bit lines can be detected through a general testing algorithm. A testing algorithm is intended for obtaining the maximum coverage of a defect model with the least testing actions. Accordingly, even though a general testing algorithm can provide correct defect locations, the defect locations may not be complete. For example, if there is a short circuit defect between the bit lines of two bits, a testing algorithm may detect only one defective bit instead of two. In this case, only a portion of all defects are repaired if the defects are repaired according to such a testing result.
Accordingly, a general testing algorithm provides incorrect location information of defects between word lines and insufficient location information of defects between bit lines. In conclusion, a reliable BISR technique for repairing port-specific faults in a multi-port memory is required.